The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose des techniques d'amélioration de la résolution pour les convertisseurs analogique-numérique (CAN) pipelines multi-étages à grande vitesse, basés sur un convertisseur numérique-analogique multiplicateur multi-bits/étages. Les techniques proposées augmentent la résolution du CAN et minimisent simultanément la surface de la puce, la dissipation de puissance et la complexité du circuit en supprimant la procédure de calcul au prorata du gain, qui est requise dans les CAN multi-étages calibrés numériquement conventionnels pour réduire les erreurs de gain inévitables entre les étages avec plus de deux étages calibrés. . La résolution du CAN proposé peut en outre être étendue en combinant un schéma de commutation de condensateur à rétroaction commutée conventionnel avec l'auto-étalonnage dans le domaine numérique.
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Joon-Seok LEE, Se-Hoon JOO, Seung-Hoon LEE, "Resolution Enhancement Techniques for High-Speed Multi-Stage Pipelined ADC's Based on a Multi-Bit Multiplying DAC" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1092-1099, August 2001, doi: .
Abstract: This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1092/_p
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@ARTICLE{e84-c_8_1092,
author={Joon-Seok LEE, Se-Hoon JOO, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Resolution Enhancement Techniques for High-Speed Multi-Stage Pipelined ADC's Based on a Multi-Bit Multiplying DAC},
year={2001},
volume={E84-C},
number={8},
pages={1092-1099},
abstract={This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Resolution Enhancement Techniques for High-Speed Multi-Stage Pipelined ADC's Based on a Multi-Bit Multiplying DAC
T2 - IEICE TRANSACTIONS on Electronics
SP - 1092
EP - 1099
AU - Joon-Seok LEE
AU - Se-Hoon JOO
AU - Seung-Hoon LEE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.
ER -