The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit un convertisseur analogique-numérique (CAN) à sous-gamme CMOS 8b 52 MHz pour les applications de boucle d'abonné numérique. L'ADC proposé, basé sur une architecture améliorée à entrelacement temporel, supprime le temps de maintien qui est généralement observé dans les ADC à sous-gamme à double canal conventionnels pour augmenter le débit de 50 %. L'ADC utilise la technique d'interpolation dans les ADC de sous-gamme back-end pour le traitement du signal résiduel afin de minimiser la zone de puce active et la consommation d'énergie. Une technique de configuration est adoptée pour réduire les décalages du comparateur induits par le plasma et la zone de puce de l'ADC. Le prototype d'ADC fabriqué et mesuré dans un processus CMOS de 0.8 µm montre des non-linéarités inférieures à
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Sung-Ho LEE, Jung-Woong MOON, Seung-Hoon LEE, "An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 4, pp. 470-474, April 2001, doi: .
Abstract: This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_4_470/_p
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@ARTICLE{e84-c_4_470,
author={Sung-Ho LEE, Jung-Woong MOON, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications},
year={2001},
volume={E84-C},
number={4},
pages={470-474},
abstract={This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 470
EP - 474
AU - Sung-Ho LEE
AU - Jung-Woong MOON
AU - Seung-Hoon LEE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2001
AB - This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than
ER -