The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article décrit des techniques permettant d'élargir les plages de verrouillage et d'extraction et de supprimer la gigue dans les circuits intégrés d'horloge et de récupération de données. Il est montré théoriquement que l'utilisation d'une technique de boucle à verrouillage de phase (PLL) à commande de boucle dupliquée (DLC) permet des plages de verrouillage et d'extraction plus larges dans la récupération d'horloge et de données (CDR) sans augmenter la fréquence de coupure de la fonction de transfert de gigue. . Un circuit intégré DLC-CDR de 2.5 Gb/s fabriqué avec un processus bipolaire Si de 0.5 µm offre 2.5 fois la plage de verrouillage et 1.5 fois la plage d'attraction d'un circuit intégré CDR classique, et les caractéristiques de gigue du circuit intégré CDR fabriqué répondent à toutes les exigences. trois spécifications de gigue STM-16 dans la recommandation ITU-T G.958.
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Copier
Keiji KISHINE, Noboru ISHIHARA, Haruhiko ICHINO, "Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 4, pp. 460-469, April 2001, doi: .
Abstract: This paper describes techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) technique enables wider lock and pull-in ranges in clock and data recovery (CDR) without increasing the cut-off frequency of the jitter transfer function. A 2.5-Gb/s DLC-CDR IC fabricated with a 0.5-µm Si bipolar process provides 2.5 times the lock range and 1.5 times the pull-in range of a conventional CDR IC, and the jitter characteristics of the fabricated CDR IC meet all three STM-16 jitter specifications in ITU-T recommendation G.958.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_4_460/_p
Copier
@ARTICLE{e84-c_4_460,
author={Keiji KISHINE, Noboru ISHIHARA, Haruhiko ICHINO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--},
year={2001},
volume={E84-C},
number={4},
pages={460-469},
abstract={This paper describes techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) technique enables wider lock and pull-in ranges in clock and data recovery (CDR) without increasing the cut-off frequency of the jitter transfer function. A 2.5-Gb/s DLC-CDR IC fabricated with a 0.5-µm Si bipolar process provides 2.5 times the lock range and 1.5 times the pull-in range of a conventional CDR IC, and the jitter characteristics of the fabricated CDR IC meet all three STM-16 jitter specifications in ITU-T recommendation G.958.},
keywords={},
doi={},
ISSN={},
month={April},}
Copier
TY - JOUR
TI - Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--
T2 - IEICE TRANSACTIONS on Electronics
SP - 460
EP - 469
AU - Keiji KISHINE
AU - Noboru ISHIHARA
AU - Haruhiko ICHINO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2001
AB - This paper describes techniques for widening lock and pull-in ranges and suppressing jitter in clock and data recovery ICs. It is shown theoretically that using a duplicated loop control (DLC)-phase-locked loop (PLL) technique enables wider lock and pull-in ranges in clock and data recovery (CDR) without increasing the cut-off frequency of the jitter transfer function. A 2.5-Gb/s DLC-CDR IC fabricated with a 0.5-µm Si bipolar process provides 2.5 times the lock range and 1.5 times the pull-in range of a conventional CDR IC, and the jitter characteristics of the fabricated CDR IC meet all three STM-16 jitter specifications in ITU-T recommendation G.958.
ER -