The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'invention concerne une puce qui intègre deux cœurs de processeur multimédia VLIW avec un moteur de streaming matériel. Il peut mettre en œuvre un visiophone en temps réel, ou un codec MPEG4. Chaque cœur de processeur dispose de ressources identiques et partage la mémoire et les unités d'interface d'E/S système. Grâce à sa structure symétrique, les applications peuvent être exécutées sur l'un ou l'autre processeur sans contraintes. Pour accélérer les applications spécifiques au multimédia, l'architecture de ce processeur présente plusieurs fonctionnalités. Il fusionne les fonctionnalités d'un RISC et d'un DSP, son jeu d'instructions est étendu pour accélérer les applications vidéo et audio, et il prend en charge un système de mémoire intégré efficace, afin de réduire à la fois la bande passante et la latence pour les applications multimédia nécessitant des accès fréquents à la mémoire. La taille des copeaux sera de 100 mm2 puce contenant 700 K portes logiques, 60 Ko de RAM et 16 Ko de ROM, dans une technologie de cellule standard CMOS de 0.25 µm. À une fréquence de fonctionnement de 65 MHz, il peut traiter le codage vidéo H.263 à CIF 15 images/s et le codage audio G.723.1 avec une allocation de temps de traitement de 80 %.
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Jeong-Min KIM, Yun-Su SHIN, In-Gu HWANG, Kwang-Sun LEE, Sang-Il HAN, Sang-Gyu PARK, Soo-Ik CHAE, "A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 183-192, February 2001, doi: .
Abstract: A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_183/_p
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@ARTICLE{e84-c_2_183,
author={Jeong-Min KIM, Yun-Su SHIN, In-Gu HWANG, Kwang-Sun LEE, Sang-Il HAN, Sang-Gyu PARK, Soo-Ik CHAE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores},
year={2001},
volume={E84-C},
number={2},
pages={183-192},
abstract={A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.},
keywords={},
doi={},
ISSN={},
month={February},}
Copier
TY - JOUR
TI - A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores
T2 - IEICE TRANSACTIONS on Electronics
SP - 183
EP - 192
AU - Jeong-Min KIM
AU - Yun-Su SHIN
AU - In-Gu HWANG
AU - Kwang-Sun LEE
AU - Sang-Il HAN
AU - Sang-Gyu PARK
AU - Soo-Ik CHAE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.
ER -