The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un encodeur vidéo, audio et système MPEG-2 monopuce LSI a été développé. Il effectue un traitement simultané en temps réel de l'encodage vidéo MPEG-2 422P@ML, de l'encodage audio Dolby Digital ou MPEG-2 à 1 canaux et de l'encodage système qui génère un flux de transport multiplexé (TS) ou un flux de programme (PS). L'architecture hybride avancée, qui combine un processeur multimédia VLIW D30V hautes performances et des circuits de traitement vidéo câblés, a été adoptée pour satisfaire les exigences d'une grande flexibilité et d'une énorme capacité de calcul. Un schéma de contrôle unifié a été récemment proposé qui gère hiérarchiquement le contrôle adaptatif de la priorité des tâches sur les processus de codage vidéo, audio et système asynchrones afin d'obtenir un traitement simultané en temps réel à l'aide d'un seul D30V. Deux cœurs d'estimation de mouvement dédiés, composés d'un cœur ME grossier (CME) pour les recherches à large portée et d'un cœur ME fin (FME) pour les recherches précises, ont été intégrés pour produire une qualité d'image élevée tout en utilisant une petite quantité de matériel. Adoptant ces caractéristiques, un encodeur monopuce a été fabriqué à l'aide de la technologie CMOS métallique à 0.25 couches de 4 micron et intégré dans un boîtier de 14.2 mm.
Tetsuya MATSUMURA
Satoshi KUMAKI
Hiroshi SEGAWA
Kazuya ISHIHARA
Atsuo HANAMI
Yoshinori MATSUURA
Stefan SCOTZNIOVSKY
Hidehiro TAKATA
Akira YAMADA
Shu MURAYAMA
Tetsuro WADA
Hideo OHIRA
Toshiaki SHIMADA
Ken-ichi ASANO
Toyohiko YOSHIDA
Masahiko YOSHIMOTO
Koji TSUCHIHASHI
Yasutaka HORIBA
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Tetsuya MATSUMURA, Satoshi KUMAKI, Hiroshi SEGAWA, Kazuya ISHIHARA, Atsuo HANAMI, Yoshinori MATSUURA, Stefan SCOTZNIOVSKY, Hidehiro TAKATA, Akira YAMADA, Shu MURAYAMA, Tetsuro WADA, Hideo OHIRA, Toshiaki SHIMADA, Ken-ichi ASANO, Toyohiko YOSHIDA, Masahiko YOSHIMOTO, Koji TSUCHIHASHI, Yasutaka HORIBA, "A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 1, pp. 108-122, January 2001, doi: .
Abstract: A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_1_108/_p
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@ARTICLE{e84-c_1_108,
author={Tetsuya MATSUMURA, Satoshi KUMAKI, Hiroshi SEGAWA, Kazuya ISHIHARA, Atsuo HANAMI, Yoshinori MATSUURA, Stefan SCOTZNIOVSKY, Hidehiro TAKATA, Akira YAMADA, Shu MURAYAMA, Tetsuro WADA, Hideo OHIRA, Toshiaki SHIMADA, Ken-ichi ASANO, Toyohiko YOSHIDA, Masahiko YOSHIMOTO, Koji TSUCHIHASHI, Yasutaka HORIBA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores},
year={2001},
volume={E84-C},
number={1},
pages={108-122},
abstract={A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm
keywords={},
doi={},
ISSN={},
month={January},}
Copier
TY - JOUR
TI - A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores
T2 - IEICE TRANSACTIONS on Electronics
SP - 108
EP - 122
AU - Tetsuya MATSUMURA
AU - Satoshi KUMAKI
AU - Hiroshi SEGAWA
AU - Kazuya ISHIHARA
AU - Atsuo HANAMI
AU - Yoshinori MATSUURA
AU - Stefan SCOTZNIOVSKY
AU - Hidehiro TAKATA
AU - Akira YAMADA
AU - Shu MURAYAMA
AU - Tetsuro WADA
AU - Hideo OHIRA
AU - Toshiaki SHIMADA
AU - Ken-ichi ASANO
AU - Toyohiko YOSHIDA
AU - Masahiko YOSHIMOTO
AU - Koji TSUCHIHASHI
AU - Yasutaka HORIBA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2001
AB - A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm
ER -