The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un convertisseur A/N cyclique multibit 10 bits 3 Méch./s pour les LSI à signaux mixtes avec une petite zone de puce de 1.5 mm2 et une faible consommation d'énergie de 10.8 mW avec une alimentation de 2.7 V a été réalisée à l'aide d'un processus CMOS de 0.8 µm. Ce module ADC est conçu pour les LSI de servocontrôleur haute vitesse utilisés dans les systèmes de disque dur. Nous avons constaté que la conversion cyclique à trois cycles (quatre bits, trois bits+(un bit redondant) et trois bits+(un bit redondant)) était optimale pour atteindre une résolution de 10 bits avec une petite zone de puce et une faible consommation d'énergie compte tenu de la résolution requise. temps de conversion de 0.33 µs. Notre architecture multivoies a réduit la consommation d'énergie de 30 % par rapport aux convertisseurs A/D cycliques classiques. En ajoutant un chemin de signal entre l'amplificateur résiduel et le subADC à quatre bits, l'exigence de synchronisation de stabilisation peut être assouplie et la consommation électrique de l'amplificateur ainsi réduite.
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Tatsuji MATSUURA, Akihiro KITAGAWA, Toshiro TSUKADA, Eiki IMAIZUMI, "A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 227-235, February 2000, doi: .
Abstract: A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_227/_p
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@ARTICLE{e83-c_2_227,
author={Tatsuji MATSUURA, Akihiro KITAGAWA, Toshiro TSUKADA, Eiki IMAIZUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC},
year={2000},
volume={E83-C},
number={2},
pages={227-235},
abstract={A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC
T2 - IEICE TRANSACTIONS on Electronics
SP - 227
EP - 235
AU - Tatsuji MATSUURA
AU - Akihiro KITAGAWA
AU - Toshiro TSUKADA
AU - Eiki IMAIZUMI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.
ER -