The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Le sujet de cette étude est de proposer une nouvelle structure capable de réaliser simultanément une tension de claquage élevée et une densité de conditionnement élevée pour les interrupteurs côté bas Nch et les interrupteurs côté haut Pch dans la classe 200 V. Comme les techniques conventionnelles de relaxation du champ électrique, la structure de la plaque de champ, de l'anneau de champ et de RESURF sont bien connues, mais ces techniques sont inadéquates pour la densité de tassement élevée car ce sont des techniques en région superficielle. Pour vaincre ce sujet, il est nécessaire de détendre le champ électrique dans la région profonde. La relaxation du champ électrique a été étudiée par simulation de dispositif. Dans le commutateur côté bas Nch, le champ électrique est détendu par le film d'oxyde enfoui dans la structure SOI. Cependant, la relaxation du champ électrique ne peut pas être réalisée uniquement en adaptant la structure SOI pour le commutateur côté haut Pch. Nous avons ensuite essayé d'insérer une couche intrinsèque entre la couche de dérive P et le film d'oxyde enfoui afin d'étendre la couche d'appauvrissement dans la région profonde. Cette couche d'appauvrissement étalée par couche intrinsèque et la couche d'appauvrissement par plaque de champ se connectent verticalement, et le dosage de l'implantation ionique pour la couche de dérive peut être réglé à deux fois plus élevé que dans le cas sans couche intrinsèque. Les résultats ont révélé que la structure SOI avec couche intrinsèque est efficace pour réaliser ce sujet. De plus, en fabriquant à la fois un commutateur côté bas Nch et un commutateur côté haut Pch sur un substrat SOI intrinsèque, une tension de claquage supérieure à 250 V a été obtenue.
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Hitoshi YAMAGUCHI, Shigeyuki AKITA, Hiroaki HIMI, Kazunori KAWAMOTO, "200 V Rating CMOS Transistor Structure with Intrinsic SOI Substrate" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 12, pp. 1961-1967, December 2000, doi: .
Abstract: The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_12_1961/_p
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@ARTICLE{e83-c_12_1961,
author={Hitoshi YAMAGUCHI, Shigeyuki AKITA, Hiroaki HIMI, Kazunori KAWAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={200 V Rating CMOS Transistor Structure with Intrinsic SOI Substrate},
year={2000},
volume={E83-C},
number={12},
pages={1961-1967},
abstract={The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.},
keywords={},
doi={},
ISSN={},
month={December},}
Copier
TY - JOUR
TI - 200 V Rating CMOS Transistor Structure with Intrinsic SOI Substrate
T2 - IEICE TRANSACTIONS on Electronics
SP - 1961
EP - 1967
AU - Hitoshi YAMAGUCHI
AU - Shigeyuki AKITA
AU - Hiroaki HIMI
AU - Kazunori KAWAMOTO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2000
AB - The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.
ER -