The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article traite d'un nouveau schéma d'horloge à faible consommation pour les circuits logiques dynamiques afin de réduire la dissipation de puissance. Bien que les schémas d'horloge conventionnels pour circuits logiques dynamiques soient principalement utilisés pour des applications à grande vitesse telles que les circuits dominos, leur courant de crête est très important en raison de la concentration de la précharge et de la décharge sur une courte période. Il est difficile pour ces systèmes d’obtenir à la fois des réductions de puissance dissipée et des performances élevées. Dans le domaine de l’ingénierie énergétique, niveler la puissance signifie diminuer la puissance de crête à crête en conservant sa quantité. Nous proposons donc un schéma de synchronisation sophistiqué nivelant la dissipation de puissance des éléments de traitement qui réduit principalement la dissipation de puissance des pilotes d’horloge. Notre schéma d'horloge proposé utilise une horloge superposée avec un contrôle de puissance à grain fin, et le courant de crête devient plus faible et la dissipation de puissance sur une courte période est nivelée sans pénalité de performance en vitesse. Le schéma proposé est appliqué à un multiplicateur matriciel de 4 bits, et les réductions de dissipation de puissance du multiplicateur et du pilote d'horloge sont mesurées par le simulateur HSPICE basé sur la technologie CMOS 0.5 µm. Il est démontré que la dissipation de puissance des pilotes d'horloge, du multiplicateur de réseau 4 bits et du total est réduite d'environ 13.2 pour cent, 2.6 pour cent et 7.0 pour cent, respectivement. En conséquence, notre schéma de synchronisation est efficace pour réduire les dissipations de puissance des pilotes d’horloge.
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Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, "A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1733-1738, November 2000, doi: .
Abstract: This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1733/_p
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@ARTICLE{e83-c_11_1733,
author={Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits},
year={2000},
volume={E83-C},
number={11},
pages={1733-1738},
abstract={This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1733
EP - 1738
AU - Hiroyuki MATSUBARA
AU - Takahiro WATANABE
AU - Tadao NAKAMURA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.
ER -