The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'invention concerne un circuit sélecteur de 40 Gbit/s compatible SCFL utilisant des diodes tunnel résonantes (RTD) et des transistors à haute mobilité électronique (HEMT). Le circuit comprend deux éléments de transition monostable-bistable (MOBILE) utilisant des RTD, un circuit HEMT NOR et un tampon de sortie HEMT basé sur une logique FET couplée à la source (SCFL). Le circuit est fabriqué en intégrant de manière monolithique des RTD et des HEMT de 0.1 µm sur un substrat InP. Le circuit fabriqué présente une nette révélation à 40 Gbit/s avec une oscillation de sortie de 800 mVp-p, ce qui est proche de l'interface IC logique à grande vitesse conventionnelle appelée SCFL.
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Kimikazu SANO, Koichi MURATA, Hideaki MATSUZAKI, "SCFL-Compatible 40-Gbit/s RTD/HEMT Selector Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 10, pp. 1690-1692, October 2000, doi: .
Abstract: An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_10_1690/_p
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@ARTICLE{e83-c_10_1690,
author={Kimikazu SANO, Koichi MURATA, Hideaki MATSUZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={SCFL-Compatible 40-Gbit/s RTD/HEMT Selector Circuit},
year={2000},
volume={E83-C},
number={10},
pages={1690-1692},
abstract={An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.},
keywords={},
doi={},
ISSN={},
month={October},}
Copier
TY - JOUR
TI - SCFL-Compatible 40-Gbit/s RTD/HEMT Selector Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 1690
EP - 1692
AU - Kimikazu SANO
AU - Koichi MURATA
AU - Hideaki MATSUZAKI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2000
AB - An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.
ER -