The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
En utilisant un modèle de réseau neuronal de type Hopfield, nous présentons un algorithme pour reconstruire des matrices de processeurs maillés 3D à l'aide de commutateurs à voie unique où des processeurs de rechange sont posés sur les six surfaces d'une matrice 3D et montrons son efficacité en termes de taux de reconstruction et de temps de calcul par ordinateur. simulation. Nous montrons ensuite comment l’algorithme peut être réalisé par un circuit neuronal numérique. Il se compose de sous-circuits permettant de trouver des chemins de compensation candidats, de décider si le système neuronal atteint un état stable et à ce moment-là, l'énergie du système est minimale, ainsi que de sous-circuits pour les neurones. Le sous-circuit de chaque neurone, y compris les autres sous-circuits, ne peut être réalisé qu'avec 16 portes et deux bascules. Étant donné que les transitions d'état se font en parallèle, le circuit sera capable de trouver très rapidement un ensemble de chemins de compensation pour un modèle de défaut en un temps inférieur à 1 µs. De plus, l'implémentation matérielle de l'algorithme conduit à réaliser un système auto-reconfigurable sans l'aide d'un ordinateur hôte.
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Itsuo TAKANAMI, Satoru NAKAMURA, Tadayoshi HORITA, "Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1678-1686, September 1999, doi: .
Abstract: Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1678/_p
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@ARTICLE{e82-c_9_1678,
author={Itsuo TAKANAMI, Satoru NAKAMURA, Tadayoshi HORITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits},
year={1999},
volume={E82-C},
number={9},
pages={1678-1686},
abstract={Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1678
EP - 1686
AU - Itsuo TAKANAMI
AU - Satoru NAKAMURA
AU - Tadayoshi HORITA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.
ER -