The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un microprocesseur intégré à la DRAM sur la même puce a le potentiel d'améliorer les performances du système en réduisant la latence de la mémoire et en améliorant la bande passante mémoire. Dans cet article, nous évaluons les performances d'un multiprocesseur monopuce intégré à la DRAM lorsque la DRAM est organisée en mémoire principale sur puce et en cache sur puce. Nous comparons les performances de cette architecture avec celles d'une puce plus conventionnelle qui ne dispose que d'un cache intégré basé sur SRAM. L'architecture basée sur DRAM avec quatre processeurs surpasse l'architecture basée sur SRAM sur les applications à virgule flottante qui sont efficacement parallélisées et disposent de grands ensembles de travail. Cette différence de performances est nettement meilleure que celle possible dans une architecture monoprocesseur basée sur DRAM, qui fonctionne à peine plus rapidement qu'une architecture basée sur SRAM sur les mêmes applications. De plus, sur les charges de travail multiprogrammées, dans lesquelles des processus indépendants sont attribués à chaque processeur dans un multiprocesseur monopuce, la large bande passante de la DRAM sur puce peut mieux gérer les conflits d'accès entre eux. Ces résultats démontrent qu'un multiprocesseur tire mieux parti de la large bande passante fournie par la DRAM intégrée qu'un monoprocesseur.
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Tadaaki YAMAUCHI, Lance HAMMOND, Oyekunle A. OLUKOTUN, Kazutami ARIMOTO, "A Single Chip Multiprocessor Integrated with High Density DRAM" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 8, pp. 1567-1577, August 1999, doi: .
Abstract: A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing memory latency and improving memory bandwidth. In this paper we evaluate the performance of a single chip multiprocessor integrated with DRAM when the DRAM is organized as on-chip main memory and as on-chip cache. We compare the performance of this architecture with that of a more conventional chip which only has SRAM-based on-chip cache. The DRAM-based architecture with four processors outperforms the SRAM-based architecture on floating point applications which are effectively parallelized and have large working sets. This performance difference is significantly better than that possible in a uniprocessor DRAM-based architecture, which performs only slightly faster than an SRAM-based architecture on the same applications. In addition, on multiprogrammed workloads, in which independent processes are assigned to every processor in a single chip multiprocessor, the large bandwidth of on-chip DRAM can handle the inter-access contention better. These results demonstrate that a multiprocessor takes better advantage of the large bandwidth provided by the on-chip DRAM than a uniprocessor.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_8_1567/_p
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@ARTICLE{e82-c_8_1567,
author={Tadaaki YAMAUCHI, Lance HAMMOND, Oyekunle A. OLUKOTUN, Kazutami ARIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single Chip Multiprocessor Integrated with High Density DRAM},
year={1999},
volume={E82-C},
number={8},
pages={1567-1577},
abstract={A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing memory latency and improving memory bandwidth. In this paper we evaluate the performance of a single chip multiprocessor integrated with DRAM when the DRAM is organized as on-chip main memory and as on-chip cache. We compare the performance of this architecture with that of a more conventional chip which only has SRAM-based on-chip cache. The DRAM-based architecture with four processors outperforms the SRAM-based architecture on floating point applications which are effectively parallelized and have large working sets. This performance difference is significantly better than that possible in a uniprocessor DRAM-based architecture, which performs only slightly faster than an SRAM-based architecture on the same applications. In addition, on multiprogrammed workloads, in which independent processes are assigned to every processor in a single chip multiprocessor, the large bandwidth of on-chip DRAM can handle the inter-access contention better. These results demonstrate that a multiprocessor takes better advantage of the large bandwidth provided by the on-chip DRAM than a uniprocessor.},
keywords={},
doi={},
ISSN={},
month={August},}
Copier
TY - JOUR
TI - A Single Chip Multiprocessor Integrated with High Density DRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 1567
EP - 1577
AU - Tadaaki YAMAUCHI
AU - Lance HAMMOND
AU - Oyekunle A. OLUKOTUN
AU - Kazutami ARIMOTO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1999
AB - A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing memory latency and improving memory bandwidth. In this paper we evaluate the performance of a single chip multiprocessor integrated with DRAM when the DRAM is organized as on-chip main memory and as on-chip cache. We compare the performance of this architecture with that of a more conventional chip which only has SRAM-based on-chip cache. The DRAM-based architecture with four processors outperforms the SRAM-based architecture on floating point applications which are effectively parallelized and have large working sets. This performance difference is significantly better than that possible in a uniprocessor DRAM-based architecture, which performs only slightly faster than an SRAM-based architecture on the same applications. In addition, on multiprogrammed workloads, in which independent processes are assigned to every processor in a single chip multiprocessor, the large bandwidth of on-chip DRAM can handle the inter-access contention better. These results demonstrate that a multiprocessor takes better advantage of the large bandwidth provided by the on-chip DRAM than a uniprocessor.
ER -