The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, un multiplicateur analogique à quatre quadrants composé de quatre transistors neurones-MOS et de deux résistances de charge est proposé. Le multiplicateur proposé peut fonctionner à seulement 1 V. De plus, la plage d'entrée du multiplicateur est égale à 100 % de la tension d'alimentation. La distorsion harmonique théorique provoquée par la dégradation de la mobilité et les inadéquations des appareils est dérivée en détail. Les performances du multiplicateur proposé sont caractérisées par des simulations HSPICE avec un processus CMOS standard de 2.0 µm avec une double couche poly. Les simulations du multiplicateur proposé démontrent qu'une erreur de linéarité de 0.77 % et une distorsion harmonique totale de 0.62 % sont obtenues avec des conditions d'entrée à grande échelle. La consommation électrique maximale et
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Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, "A 1-V, 1-Vp-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 5, pp. 750-757, May 1999, doi: .
Abstract: In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_5_750/_p
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@ARTICLE{e82-c_5_750,
author={Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1-V, 1-Vp-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors},
year={1999},
volume={E82-C},
number={5},
pages={750-757},
abstract={In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and
keywords={},
doi={},
ISSN={},
month={May},}
Copier
TY - JOUR
TI - A 1-V, 1-Vp-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 750
EP - 757
AU - Koichi TANNO
AU - Okihiko ISHIZUKA
AU - Zheng TANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1999
AB - In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and
ER -