The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nouvelles structures de test pour évaluer la capacité d'isolement (CTS) et la tension de claquage d'isolement (BVCCO) a été développé. À l’aide de ces structures de test, nous avons examiné la limite d’échelle de la largeur et la structure des rainures en U à isolation étroite pour les LSI à grande vitesse et haute densité. Nous avons séparé la capacité CTS en deux composants, CTSS (composant inférieur) et CTSL (composant périphérique), et analysé l'effet de la structure du dispositif (largeur d'isolation et matériaux de remplissage) sur CTS. Nous avons constaté que la largeur minimale de la rainure en U d'isolation est particulièrement limitée par la capacité d'isolation accrue entre les N voisins.+ couches enterrées. La largeur minimale est d'environ 0.3 µm même lorsque SiO2 est utilisé comme matériau de remplissage. Nous avons donc développé une méthode efficace pour surmonter cette limitation. L’utilisation d’une structure à double tranchée et/ou d’un substrat SOI répond à l’exigence. Une structure à double tranchée peut réduire CTS de plus de 50 %, tandis que les substrats SOI donnent une réduction CTS, haute BVCCO, une immunité élevée aux rayons α et des étapes de processus réduites.
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Yoichi TAMAKI, Takashi HASHIMOTO, "New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 4, pp. 612-617, April 1999, doi: .
Abstract: New test structures for evaluating isolation capacitance (CTS) and isolation breakdown voltage (BVCCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance CTS into two components, CTSS (bottom component) and CTSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on CTS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N+ buried layers. The minimum width is about 0.3 µm even when SiO2 is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce CTS by more than 50%, while SOI substrates gives reduced CTS, high BVCCO, high α-ray immunity, and reduced process steps.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_4_612/_p
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@ARTICLE{e82-c_4_612,
author={Yoichi TAMAKI, Takashi HASHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure},
year={1999},
volume={E82-C},
number={4},
pages={612-617},
abstract={New test structures for evaluating isolation capacitance (CTS) and isolation breakdown voltage (BVCCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance CTS into two components, CTSS (bottom component) and CTSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on CTS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N+ buried layers. The minimum width is about 0.3 µm even when SiO2 is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce CTS by more than 50%, while SOI substrates gives reduced CTS, high BVCCO, high α-ray immunity, and reduced process steps.},
keywords={},
doi={},
ISSN={},
month={April},}
Copier
TY - JOUR
TI - New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure
T2 - IEICE TRANSACTIONS on Electronics
SP - 612
EP - 617
AU - Yoichi TAMAKI
AU - Takashi HASHIMOTO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1999
AB - New test structures for evaluating isolation capacitance (CTS) and isolation breakdown voltage (BVCCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance CTS into two components, CTSS (bottom component) and CTSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on CTS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N+ buried layers. The minimum width is about 0.3 µm even when SiO2 is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce CTS by more than 50%, while SOI substrates gives reduced CTS, high BVCCO, high α-ray immunity, and reduced process steps.
ER -