The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un circuit d'interface d'entrée ECL asymétrique de référence dynamique à grande vitesse a été fabriqué pour les MCM de commutation ATM avancés. Pour augmenter la limite du nombre de broches d'E/S, ce circuit fonctionne avec un signal de référence directement généré à partir du signal d'entrée lui-même. Le niveau de référence est modifié de manière dynamique pour obtenir une plus grande marge de bruit de fonctionnement. Les résultats expérimentaux montrent qu'un fonctionnement jusqu'à 3.4 Gbit/s avec une marge de niveau importante peut être atteint. Nous déployons ce circuit sur les LSI d'interface d'entrée d'un MCM de commutation ATM à 80 Gbit/s.
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Ryusuke KAWANO, Naoaki YAMANAKA, Eiji OKI, Tomoaki KAWAMURA, "A Dynamic Reference Single-Ended ECL Input Interface Circuit for MCM-Based 80-Gbps ATM Switch" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 3, pp. 519-525, March 1999, doi: .
Abstract: A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_3_519/_p
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@ARTICLE{e82-c_3_519,
author={Ryusuke KAWANO, Naoaki YAMANAKA, Eiji OKI, Tomoaki KAWAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Dynamic Reference Single-Ended ECL Input Interface Circuit for MCM-Based 80-Gbps ATM Switch},
year={1999},
volume={E82-C},
number={3},
pages={519-525},
abstract={A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.},
keywords={},
doi={},
ISSN={},
month={March},}
Copier
TY - JOUR
TI - A Dynamic Reference Single-Ended ECL Input Interface Circuit for MCM-Based 80-Gbps ATM Switch
T2 - IEICE TRANSACTIONS on Electronics
SP - 519
EP - 525
AU - Ryusuke KAWANO
AU - Naoaki YAMANAKA
AU - Eiji OKI
AU - Tomoaki KAWAMURA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1999
AB - A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.
ER -