The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un modèle analytique de la marge de bruit statique (SNM) pour une SRAM CMOS 6T adapté à l'étude de l'effet du hasard Vth la variation est dérivée. Une approche en trois étapes utilisant les points caractéristiques de la courbe de transfert de l'onduleur demi-cellule est développée. Les paramètres de chaque transistor sont traités individuellement afin que leurs sensibilités soient calculables. Un nouveau modèle MOSFET en inversion modérée est proposé pour maintenir la précision, même dans les basses températures. VDD condition. La corrélation entre les calculs du modèle proposé et les simulations de circuits a été vérifiée à l'aide d'un dispositif CMOS LSTP à 90 nm. Dépendance étroitement corrélée à des paramètres tels que Vth, W rapport, et VDD ont été obtenus. Erreur maximale mesurée dans le VDD la plage de 0.6 à 1.6 V était de 16 mV (7 % du SNM typique). Enfin, les lignes directrices pour obtenir un grand SNM sont discutées dans cet article.
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Hirofumi SHINOHARA, Koji NII, Hidetoshi ONODERA, "Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1488-1500, September 2008, doi: 10.1093/ietele/e91-c.9.1488.
Abstract: An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1488/_p
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@ARTICLE{e91-c_9_1488,
author={Hirofumi SHINOHARA, Koji NII, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration},
year={2008},
volume={E91-C},
number={9},
pages={1488-1500},
abstract={An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.},
keywords={},
doi={10.1093/ietele/e91-c.9.1488},
ISSN={1745-1353},
month={September},}
Copier
TY - JOUR
TI - Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
T2 - IEICE TRANSACTIONS on Electronics
SP - 1488
EP - 1500
AU - Hirofumi SHINOHARA
AU - Koji NII
AU - Hidetoshi ONODERA
PY - 2008
DO - 10.1093/ietele/e91-c.9.1488
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low VDD condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as Vth, the W ratio, and VDD were obtained. Maximum error measured in the VDD range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.
ER -