The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les technologies de semi-conducteurs submicroniques profonds rendront impossible la conception du pire des cas, car elles ne peuvent pas fournir les marges de conception nécessaires. Nous étudions une méthodologie de conception de cas typique, que nous appelons Constructive Timing Violation (CTV). Cet article étend le concept CTV pour réduire les instructions dépendantes, ce qui entraîne une amélioration des performances. Sur la base de simulations détaillées, nous constatons que le mécanisme proposé effondre efficacement les instructions dépendantes.
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Toshinori SATO, "A Simple Mechanism for Collapsing Instructions under Timing Speculation" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1394-1401, September 2008, doi: 10.1093/ietele/e91-c.9.1394.
Abstract: The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1394/_p
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@ARTICLE{e91-c_9_1394,
author={Toshinori SATO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Simple Mechanism for Collapsing Instructions under Timing Speculation},
year={2008},
volume={E91-C},
number={9},
pages={1394-1401},
abstract={The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.},
keywords={},
doi={10.1093/ietele/e91-c.9.1394},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - A Simple Mechanism for Collapsing Instructions under Timing Speculation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1394
EP - 1401
AU - Toshinori SATO
PY - 2008
DO - 10.1093/ietele/e91-c.9.1394
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.
ER -