The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article présente l'architecture du processeur qui offre un niveau de fiabilité bien supérieur à celui actuel. Ses caractéristiques sont les suivantes : (1) la tolérance aux pannes et le traitement sécurisé sont intégrés dans un processeur VLSI superscalaire moderne ; (2) des mécanismes légers et efficaces tolérants aux erreurs logicielles sont proposés et évalués ; (3) les erreurs de synchronisation sur la logique aléatoire et les registres sont évitées par des mécanismes à faible surcharge ; (4) le comportement du programme est caché au monde extérieur par les méthodes de traduction d'adresse proposées ; (5) les fuites d'informations peuvent être évitées en attachant des balises de stratégie pour toutes les données et en les surveillant pour chaque exécution d'instruction ; (6) les attaques par injection sont évitées avec une précision beaucoup plus élevée que les systèmes actuels, en fournissant un suivi des balises ; (7) la structure globale du processeur fiable est proposée avec un responsable de la fiabilité qui contrôle la détection de conditions illégales et revient au mode normal ; et (8) un système de banc d'essai basé sur FPGA est développé dans lequel l'horloge système et la tension sont intentionnellement modifiées à des fins d'expérimentation. L'article présente le schéma fondamental de la fiabilité, les technologies élémentaires pour la fiabilité et l'architecture entière du processeur ultra fiable. Après les avoir montrés, l'article se termine par les travaux futurs.
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Shuichi SAKAI, Masahiro GOSHIMA, Hidetsugu IRIE, "Ultra Dependable Processor" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1386-1393, September 2008, doi: 10.1093/ietele/e91-c.9.1386.
Abstract: This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1386/_p
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@ARTICLE{e91-c_9_1386,
author={Shuichi SAKAI, Masahiro GOSHIMA, Hidetsugu IRIE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ultra Dependable Processor},
year={2008},
volume={E91-C},
number={9},
pages={1386-1393},
abstract={This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.},
keywords={},
doi={10.1093/ietele/e91-c.9.1386},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - Ultra Dependable Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 1386
EP - 1393
AU - Shuichi SAKAI
AU - Masahiro GOSHIMA
AU - Hidetsugu IRIE
PY - 2008
DO - 10.1093/ietele/e91-c.9.1386
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.
ER -