The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une technologie optimisée d’auto-test intégré est proposée dans cet article. Un modèle algébrique simplifié est développé pour représenter les configurations de circuits de changement à entrée unique. Une nouvelle technique de génération de séquence de changement à entrée unique est conçue. Il se compose d'un registre à décalage de balayage modifié, d'un réseau de stockage de graines et d'une série de portes XOR. Ce circuit peut générer automatiquement des séquences de changement d'entrée unique de vecteurs plus uniques. Les résultats expérimentaux basés sur le benchmark ISCAS-89 montrent que la méthode proposée peut atteindre une couverture élevée des défauts bloqués avec une faible activité de commutation pendant les applications de test.
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Feng LIANG, ShaoChong LEI, ZhiBiao SHAO, "A Single Input Change Test Pattern Generator for Sequential Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 8, pp. 1365-1370, August 2008, doi: 10.1093/ietele/e91-c.8.1365.
Abstract: An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.8.1365/_p
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@ARTICLE{e91-c_8_1365,
author={Feng LIANG, ShaoChong LEI, ZhiBiao SHAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single Input Change Test Pattern Generator for Sequential Circuits},
year={2008},
volume={E91-C},
number={8},
pages={1365-1370},
abstract={An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.},
keywords={},
doi={10.1093/ietele/e91-c.8.1365},
ISSN={1745-1353},
month={August},}
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TY - JOUR
TI - A Single Input Change Test Pattern Generator for Sequential Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1365
EP - 1370
AU - Feng LIANG
AU - ShaoChong LEI
AU - ZhiBiao SHAO
PY - 2008
DO - 10.1093/ietele/e91-c.8.1365
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2008
AB - An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
ER -