The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Un nouveau générateur d'horloge à spectre étalé (SSCG) utilisant une modulation delta-sigma à deux points est présenté dans cet article. Non seulement le diviseur varie, mais l'oscillateur contrôlé en tension est également modulé. Cette technique peut améliorer la bande passante de modulation de sorte que l'effet de suppression EMI soit amélioré avec un modulateur ΣΔ d'ordre inférieur et peut simultanément optimiser la gigue et le profil de modulation. De plus, la méthode des deux trajets est appliquée au filtre en boucle pour réduire la valeur de capacité de telle sorte que l'intégration totale puisse être obtenue. Le SSCG proposé a été fabriqué selon un processus CMOS de 0.35 µm. L'horloge de 400 MHz avec des rapports d'étalement central de 1.25 % et 2.5 % est vérifiée. La réduction maximale des EMI est de 19.73 dB pour le cas de 2.5 %. La taille de la zone de puce est de 0.90
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Yao-Huang KAO, Yi-Bin HSIEH, "A High Performance Spread Spectrum Clock Generator Using Two-Point Modulation Scheme" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 6, pp. 911-917, June 2008, doi: 10.1093/ietele/e91-c.6.911.
Abstract: A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order ΣΔ modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 µm CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.90
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.6.911/_p
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@ARTICLE{e91-c_6_911,
author={Yao-Huang KAO, Yi-Bin HSIEH, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High Performance Spread Spectrum Clock Generator Using Two-Point Modulation Scheme},
year={2008},
volume={E91-C},
number={6},
pages={911-917},
abstract={A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order ΣΔ modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 µm CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.90
keywords={},
doi={10.1093/ietele/e91-c.6.911},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - A High Performance Spread Spectrum Clock Generator Using Two-Point Modulation Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 911
EP - 917
AU - Yao-Huang KAO
AU - Yi-Bin HSIEH
PY - 2008
DO - 10.1093/ietele/e91-c.6.911
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2008
AB - A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order ΣΔ modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 µm CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.90
ER -