The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Pour les récepteurs sans fil, les CAN pipeline basse consommation 1.2 V 12 bits 100 MSPS sont fabriqués en technologie CMOS 90 nm. Pour obtenir une faible dissipation de puissance à 1.2 V sans dégradation du SNR, la configuration de 2.5 bits/étage est utilisée avec une technique de partage d'amplificateur I/Q. De plus, des amplificateurs pseudo-différentiels à un étage sont utilisés dans un circuit d'échantillonnage et de maintien (S/H) et un premier convertisseur numérique-analogique multiplicateur (MDAC). L'amplificateur pseudo-différentiel doté d'amplificateurs d'amplification de gain de transimpédance à deux étages de gain réalise un gain CC élevé de plus de 1 dB avec une faible puissance. Le SNR mesuré du CAN 90 MSPS est de 100 dB à une alimentation de 66.7 V. Dans ces conditions, chaque CAN ne dissipe que 1.2 mW.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copier
Tomohiko ITO, Daisuke KUROSE, Takeshi UENO, Takafumi YAMAJI, Tetsuro ITAKURA, "55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 6, pp. 887-893, June 2008, doi: 10.1093/ietele/e91-c.6.887.
Abstract: For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.6.887/_p
Copier
@ARTICLE{e91-c_6_887,
author={Tomohiko ITO, Daisuke KUROSE, Takeshi UENO, Takafumi YAMAJI, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers},
year={2008},
volume={E91-C},
number={6},
pages={887-893},
abstract={For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.},
keywords={},
doi={10.1093/ietele/e91-c.6.887},
ISSN={1745-1353},
month={June},}
Copier
TY - JOUR
TI - 55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
T2 - IEICE TRANSACTIONS on Electronics
SP - 887
EP - 893
AU - Tomohiko ITO
AU - Daisuke KUROSE
AU - Takeshi UENO
AU - Takafumi YAMAJI
AU - Tetsuro ITAKURA
PY - 2008
DO - 10.1093/ietele/e91-c.6.887
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2008
AB - For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5 bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage pseudo-differential amplifiers are used in a Sample-and-Hold (S/H) circuit and a 1st Multiplying Digital-to-Analog Converter (MDAC). The pseudo-differential amplifier with two-gain-stage transimpedance gain-boosting amplifiers realizes high DC gain of more than 90 dB with low power. The measured SNR of the 100-MSPS ADC is 66.7 dB at 1.2-V supply. Under that condition, each ADC dissipates only 55 mW.
ER -