The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cette lettre présente un réseau d'horloges à diffusion ponctuelle (PDCN) avec un schéma de synthèse d'arbre d'horloge locale (CTS). Le réseau d'horloge est mis en œuvre avec un espace de lignes métalliques dix fois plus large que les réseaux maillés classiques pour une faible consommation et est utilisé pour une exécution CTS de zone neuf fois plus petite pour minimiser le décalage d'horloge. Les résultats de mesure montrent que la quantité asymétrique de PDCN avec CTS local est réduite à 36 % et que la latence est réduite à 45 % de la quantité dans un écran de 4.81 mm.2 Noyau CortexA-8 avec processus Samsung 65 nm.
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Gunok JUNG, Chunghee KIM, Kyoungkuk CHAE, Giho PARK, Sung Bae PARK, "Power and Skew Aware Point Diffusion Clock Network" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 11, pp. 1832-1834, November 2008, doi: 10.1093/ietele/e91-c.11.1832.
Abstract: This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.11.1832/_p
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@ARTICLE{e91-c_11_1832,
author={Gunok JUNG, Chunghee KIM, Kyoungkuk CHAE, Giho PARK, Sung Bae PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power and Skew Aware Point Diffusion Clock Network},
year={2008},
volume={E91-C},
number={11},
pages={1832-1834},
abstract={This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.},
keywords={},
doi={10.1093/ietele/e91-c.11.1832},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - Power and Skew Aware Point Diffusion Clock Network
T2 - IEICE TRANSACTIONS on Electronics
SP - 1832
EP - 1834
AU - Gunok JUNG
AU - Chunghee KIM
AU - Kyoungkuk CHAE
AU - Giho PARK
AU - Sung Bae PARK
PY - 2008
DO - 10.1093/ietele/e91-c.11.1832
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2008
AB - This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm2 CortexA-8 core with 65 nm Samsung process.
ER -