The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une photodiode latérale en silicium est fabriquée par un procédé CMOS standard de 0.18 µm, et la propriété de détection optique est caractérisée. La photodiode a une structure d'électrode interdigitale avec une largeur d'électrode de 0.22 µm et un espacement des électrodes de 0.6 µm. À une longueur d'onde de 830 nm, la réactivité est de 0.12 A/W à faible tension de polarisation et est augmentée à 0.6 A/W en raison de l'amplification par avalanche. La bande passante est également améliorée, passant de 12 MHz à faible tension de polarisation à 100 MHz à une tension de polarisation proche de la tension de claquage.
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Koichi IIYAMA, Noriaki SANNOU, Hideki TAKAMATSU, "Avalanche Amplification in Silicon Lateral Photodiode Fabricated by Standard 0.18 µm CMOS Process" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 11, pp. 1820-1823, November 2008, doi: 10.1093/ietele/e91-c.11.1820.
Abstract: A silicon lateral photodiode is fabricated by standard 0.18 µm CMOS process, and the optical detection property is characterized. The photodiode has interdigital electrode structure with the electrode width of 0.22 µm and the electrode spacing of 0.6 µm. At 830 nm wavelength, the responsivity is 0.12 A/W at low bias voltage, and is increased to 0.6 A/W due to avalanche amplification. The bandwidth is also enhanced from 12 MHz at low bias voltage to 100 MHz at the bias voltage close to the breakdown voltage.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.11.1820/_p
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@ARTICLE{e91-c_11_1820,
author={Koichi IIYAMA, Noriaki SANNOU, Hideki TAKAMATSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Avalanche Amplification in Silicon Lateral Photodiode Fabricated by Standard 0.18 µm CMOS Process},
year={2008},
volume={E91-C},
number={11},
pages={1820-1823},
abstract={A silicon lateral photodiode is fabricated by standard 0.18 µm CMOS process, and the optical detection property is characterized. The photodiode has interdigital electrode structure with the electrode width of 0.22 µm and the electrode spacing of 0.6 µm. At 830 nm wavelength, the responsivity is 0.12 A/W at low bias voltage, and is increased to 0.6 A/W due to avalanche amplification. The bandwidth is also enhanced from 12 MHz at low bias voltage to 100 MHz at the bias voltage close to the breakdown voltage.},
keywords={},
doi={10.1093/ietele/e91-c.11.1820},
ISSN={1745-1353},
month={November},}
Copier
TY - JOUR
TI - Avalanche Amplification in Silicon Lateral Photodiode Fabricated by Standard 0.18 µm CMOS Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 1820
EP - 1823
AU - Koichi IIYAMA
AU - Noriaki SANNOU
AU - Hideki TAKAMATSU
PY - 2008
DO - 10.1093/ietele/e91-c.11.1820
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2008
AB - A silicon lateral photodiode is fabricated by standard 0.18 µm CMOS process, and the optical detection property is characterized. The photodiode has interdigital electrode structure with the electrode width of 0.22 µm and the electrode spacing of 0.6 µm. At 830 nm wavelength, the responsivity is 0.12 A/W at low bias voltage, and is increased to 0.6 A/W due to avalanche amplification. The bandwidth is also enhanced from 12 MHz at low bias voltage to 100 MHz at the bias voltage close to the breakdown voltage.
ER -