The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cet article propose un moteur matériel de mise en correspondance de modèles parallèles utilisant une architecture de correspondance de chaînes à bits divisés basée sur la mémoire. Le comparateur de chaînes à fractionnement de bits proposé sépare la table de transition de la table d'état, de sorte que les transitions d'état vers l'état initial ne soient pas stockées. Par conséquent, les besoins totaux en mémoire peuvent être minimisés.
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HyunJin KIM, Hong-Sik KIM, Jung-Hee LEE, Jin-Ho AHN, Sungho KANG, "A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection" in IEICE TRANSACTIONS on Communications,
vol. E93-B, no. 2, pp. 396-398, February 2010, doi: 10.1587/transcom.E93.B.396.
Abstract: This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E93.B.396/_p
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@ARTICLE{e93-b_2_396,
author={HyunJin KIM, Hong-Sik KIM, Jung-Hee LEE, Jin-Ho AHN, Sungho KANG, },
journal={IEICE TRANSACTIONS on Communications},
title={A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection},
year={2010},
volume={E93-B},
number={2},
pages={396-398},
abstract={This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.},
keywords={},
doi={10.1587/transcom.E93.B.396},
ISSN={1745-1345},
month={February},}
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TY - JOUR
TI - A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection
T2 - IEICE TRANSACTIONS on Communications
SP - 396
EP - 398
AU - HyunJin KIM
AU - Hong-Sik KIM
AU - Jung-Hee LEE
AU - Jin-Ho AHN
AU - Sungho KANG
PY - 2010
DO - 10.1587/transcom.E93.B.396
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E93-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2010
AB - This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.
ER -