The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'application de la virtualisation des fonctions réseau (NFV) et des réseaux définis par logiciel (SDN) aux réseaux optiques passifs (PON) attire l'attention pour le déploiement de systèmes de réseaux d'accès rentables. Cet article présente une nouvelle architecture d'une machine à états finis programmable (P-FSM) comme accélérateur matériel pour le traitement de protocole dans un terminal de ligne optique (OLT). Le P-FSM est un matériel programmable qui gère différents types de FSM pour améliorer la flexibilité des OLT et atteindre des performances filaires avec une augmentation négligeable de la surface totale de la puce. Le P-FSM est implémenté à l'aide de trois technologies clés : une architecture spécifique pour la gestion de l'état des protocoles de communication afin de minimiser la zone logique, une implémentation en mémoire distribuée pour minimiser la mémoire du programme et une nouvelle opération de branchement pour minimiser la zone mémoire et réduire le temps de traitement. . Les résultats de l'évaluation montrent que le P-FSM peut gérer les protocoles de communication 10G-EPON/NG-PON2 dans la même architecture tout en atteignant des performances filaires. L'augmentation de la surface totale conçue n'est que de 1.5 % à 4.9 % selon le nombre de protocoles pris en charge par rapport à la surface d'un SoC de communication conventionnel sans flexibilité. Nous précisons également que notre architecture a l'évolutivité nécessaire pour modifier le nombre de FSM et le nombre maximum de connexions ONU en fonction de l'échelle du système.
Saki HATTA
NTT Corporation
Nobuyuki TANAKA
NTT Corporation
Hiroyuki UZAWA
NTT Corporation
Koyo NITTA
NTT Corporation
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Saki HATTA, Nobuyuki TANAKA, Hiroyuki UZAWA, Koyo NITTA, "Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems" in IEICE TRANSACTIONS on Communications,
vol. E104-B, no. 3, pp. 277-285, March 2021, doi: 10.1587/transcom.2020EBP3050.
Abstract: The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2020EBP3050/_p
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@ARTICLE{e104-b_3_277,
author={Saki HATTA, Nobuyuki TANAKA, Hiroyuki UZAWA, Koyo NITTA, },
journal={IEICE TRANSACTIONS on Communications},
title={Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems},
year={2021},
volume={E104-B},
number={3},
pages={277-285},
abstract={The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.},
keywords={},
doi={10.1587/transcom.2020EBP3050},
ISSN={1745-1345},
month={March},}
Copier
TY - JOUR
TI - Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems
T2 - IEICE TRANSACTIONS on Communications
SP - 277
EP - 285
AU - Saki HATTA
AU - Nobuyuki TANAKA
AU - Hiroyuki UZAWA
AU - Koyo NITTA
PY - 2021
DO - 10.1587/transcom.2020EBP3050
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E104-B
IS - 3
JA - IEICE TRANSACTIONS on Communications
Y1 - March 2021
AB - The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.
ER -