The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les services avancés de traitement de l’information basés sur le cloud computing sont très demandés. Cependant, les utilisateurs souhaitent pouvoir personnaliser les services cloud en fonction de leurs propres besoins. Afin de fournir des services de traitement d'image pouvant être optimisés pour les besoins de chaque utilisateur, nous proposons une technique permettant de chaîner des fonctions de traitement d'image dans une architecture de serveur couplée à un réseau de portes programmables sur site (FPGA) CPU. L'une des exigences les plus importantes pour combiner plusieurs fonctions de traitement d'image sur un réseau est la faible latence des nœuds de serveur. Cependant, un retard important se produit dans l'architecture CPU-FPGA conventionnelle en raison des frais généraux de réorganisation des paquets pour garantir l'exactitude du traitement d'image et du transfert de données entre le CPU et le FPGA au niveau de l'application. Cet article présente une architecture de serveur CPU-FPGA avec un circuit de réorganisation des paquets en temps réel pour le traitement d'images à faible latence. Afin de confirmer l'efficacité de notre idée, nous avons évalué la latence du calcul des caractéristiques de l'histogramme des gradients orientés (HOG) en tant que fonction de traitement d'image déchargée. Les résultats montrent que la latence est environ 26 fois inférieure à celle de l'architecture CPU-FPGA conventionnelle. De plus, le débit a diminué de moins de 3.7 % dans le pire des cas, où 90 % des paquets sont échangés de manière aléatoire à un débit d'entrée de 40 Gbit/s. Enfin, nous avons démontré qu'un service de surveillance vidéo en temps réel peut être fourni en combinant des fonctions de traitement d'images utilisant notre architecture.
Yuta UKON
NTT Corporation
Koji YAMAZAKI
NTT Corporation
Koyo NITTA
NTT Corporation
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Yuta UKON, Koji YAMAZAKI, Koyo NITTA, "Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture" in IEICE TRANSACTIONS on Communications,
vol. E103-B, no. 1, pp. 11-19, January 2020, doi: 10.1587/transcom.2019CPP0001.
Abstract: Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2019CPP0001/_p
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@ARTICLE{e103-b_1_11,
author={Yuta UKON, Koji YAMAZAKI, Koyo NITTA, },
journal={IEICE TRANSACTIONS on Communications},
title={Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture},
year={2020},
volume={E103-B},
number={1},
pages={11-19},
abstract={Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.},
keywords={},
doi={10.1587/transcom.2019CPP0001},
ISSN={1745-1345},
month={January},}
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TY - JOUR
TI - Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
T2 - IEICE TRANSACTIONS on Communications
SP - 11
EP - 19
AU - Yuta UKON
AU - Koji YAMAZAKI
AU - Koyo NITTA
PY - 2020
DO - 10.1587/transcom.2019CPP0001
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E103-B
IS - 1
JA - IEICE TRANSACTIONS on Communications
Y1 - January 2020
AB - Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.
ER -