The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Les commutateurs basés sur FPGA sont aujourd'hui attrayants en raison de l'équilibre entre performances matérielles et flexibilité logicielle. L'analyseur de paquets, en tant que composant fondamental des commutateurs basés sur FPGA, consiste à identifier et à extraire des champs spécifiques utilisés dans les décisions de transfert, par exemple l'adresse IP de destination. Cependant, les analyseurs traditionnels sont trop rigides pour s'adapter aux nouveaux protocoles. De plus, les FPGA ont généralement une fréquence d'horloge beaucoup plus faible et moins de ressources matérielles que les ASIC. Dans cet article, nous présentons PLANET, une architecture d'analyse parallèle programmable au niveau des paquets pour les commutateurs basés sur FPGA, permettant de surmonter ces deux limitations. Premièrement, PLANET dispose d'une programmabilité flexible pour mettre à jour les algorithmes d'analyse au moment de l'exécution. Deuxièmement, PLANET exploite fortement le parallélisme dans l'analyse des paquets pour compenser la faible fréquence d'horloge du FPGA et réduit la consommation de ressources grâce à une conception de recyclage en un seul bloc. Nous avons implémenté PLANET sur un prototype de commutateur basé sur FPGA avec des protocoles de centre de données bien intégrés. Les résultats de l'évaluation montrent que notre conception peut analyser des paquets jusqu'à 100 Gbps, ainsi que de maintenir une latence d'analyse relativement faible et moins de ressources matérielles que les propositions existantes.
Junnan LI
National University of Defense Technology
Biao HAN
National University of Defense Technology
Zhigang SUN
National University of Defense Technology
Tao LI
National University of Defense Technology
Xiaoyan WANG
Ibaraki University
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Junnan LI, Biao HAN, Zhigang SUN, Tao LI, Xiaoyan WANG, "Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches" in IEICE TRANSACTIONS on Communications,
vol. E102-B, no. 9, pp. 1862-1874, September 2019, doi: 10.1587/transcom.2018EBP3333.
Abstract: FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2018EBP3333/_p
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@ARTICLE{e102-b_9_1862,
author={Junnan LI, Biao HAN, Zhigang SUN, Tao LI, Xiaoyan WANG, },
journal={IEICE TRANSACTIONS on Communications},
title={Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches},
year={2019},
volume={E102-B},
number={9},
pages={1862-1874},
abstract={FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.},
keywords={},
doi={10.1587/transcom.2018EBP3333},
ISSN={1745-1345},
month={September},}
Copier
TY - JOUR
TI - Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches
T2 - IEICE TRANSACTIONS on Communications
SP - 1862
EP - 1874
AU - Junnan LI
AU - Biao HAN
AU - Zhigang SUN
AU - Tao LI
AU - Xiaoyan WANG
PY - 2019
DO - 10.1587/transcom.2018EBP3333
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E102-B
IS - 9
JA - IEICE TRANSACTIONS on Communications
Y1 - September 2019
AB - FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.
ER -