The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dans cet article, nous présentons la conception et la mise en œuvre d’un VLSI de transfert Ethernet sur HDLC rentable pour le système d’accès réseau. Il prend en charge les PHY Ethernet 10/100 Mbps et l'interface HDLC jusqu'à 50 Mbps directement appliquée au modem ou à l'émetteur-récepteur. Le taux de transfert/filtrage maximum est de 90,000 1 pps avec une latence de débit de 0.5 image, ce qui prend en charge les applications à grande vitesse. Il peut également prendre en charge le mode maître pour Ethernet PHY et le mode esclave pour changer de puce par la configuration des broches. Il a été implémenté sous la forme d'une puce unique basée sur la technologie CMOS XNUMX µm. Les tests sur le terrain montrent que le transfert et le traitement des paquets à vitesse filaire grâce à la puce implémentée peuvent être obtenus.
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Minsuk HONG, Jinsung OH, Chan Young PARK, Wooseok KANG, Sehyeon RHEE, Sang-Hui PARK, "Ethernet Over HDLC Forwarding VLSI for Network Access System" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 7, pp. 1382-1385, July 2002, doi: .
Abstract: In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_7_1382/_p
Copier
@ARTICLE{e85-b_7_1382,
author={Minsuk HONG, Jinsung OH, Chan Young PARK, Wooseok KANG, Sehyeon RHEE, Sang-Hui PARK, },
journal={IEICE TRANSACTIONS on Communications},
title={Ethernet Over HDLC Forwarding VLSI for Network Access System},
year={2002},
volume={E85-B},
number={7},
pages={1382-1385},
abstract={In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.},
keywords={},
doi={},
ISSN={},
month={July},}
Copier
TY - JOUR
TI - Ethernet Over HDLC Forwarding VLSI for Network Access System
T2 - IEICE TRANSACTIONS on Communications
SP - 1382
EP - 1385
AU - Minsuk HONG
AU - Jinsung OH
AU - Chan Young PARK
AU - Wooseok KANG
AU - Sehyeon RHEE
AU - Sang-Hui PARK
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 2002
AB - In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.
ER -