The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une nouvelle approche pour construire un système multitraitement en temps réel dont la configuration est flexible pour évaluer les égaliseurs espace-temps (ST) est décrite. Le cœur du système est constitué de dispositifs entièrement programmables tels que des processeurs de signaux numériques (DSP), des réseaux de portes programmables sur site (FPGA) et des ordinateurs à jeu d'instructions réduit (RISC) dotés d'un système d'exploitation en temps réel (RTOS). Le RTOS facilite la flexibilité dans la configuration multiprocesseur pour le système conforme aux algorithmes de traitement ST. La synchronisation de la gigue temporelle provoquée par l'utilisation du système intégré RTOS est présentée, et un format de trame réglable pour un système de transmission est décrit comme une mesure permettant d'éviter le problème de gigue. Les performances du taux d'erreur sur les bits (BER) mesurées dans des canaux d'évanouissement sélectifs en fréquence non corrélés montrent qu'un égaliseur ST fournit un BER nettement inférieur à celui d'un processeur matriciel.
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Takeshi TODA, Masaaki FUJII, "Real-Time Multiprocessing System for Space-Time Equalizer in High Data Rate TDMA Mobile Wireless Communications" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 12, pp. 2716-2725, December 2002, doi: .
Abstract: A new approach to build up a real-time multiprocessing system that is configuration flexible for evaluating space-time (ST) equalizers is described. The core of the system consists of fully programmable devices such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and reduced instruction set computers (RISCs) with a real-time operating system (RTOS). The RTOS facilitates flexibility in the multi-processor configuration for the system conforming with ST processing algorithms. Timing jitter synchronization caused by use of the RTOS-embedded system is shown, and an adjustable frame format for a transmission system is described as a measure to avoid the jitter problem. Bit error rate (BER) performances measured in uncorrelated frequency-selective fading channels show that an ST equalizer provides a significantly lower BER than an array processor does.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_12_2716/_p
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@ARTICLE{e85-b_12_2716,
author={Takeshi TODA, Masaaki FUJII, },
journal={IEICE TRANSACTIONS on Communications},
title={Real-Time Multiprocessing System for Space-Time Equalizer in High Data Rate TDMA Mobile Wireless Communications},
year={2002},
volume={E85-B},
number={12},
pages={2716-2725},
abstract={A new approach to build up a real-time multiprocessing system that is configuration flexible for evaluating space-time (ST) equalizers is described. The core of the system consists of fully programmable devices such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and reduced instruction set computers (RISCs) with a real-time operating system (RTOS). The RTOS facilitates flexibility in the multi-processor configuration for the system conforming with ST processing algorithms. Timing jitter synchronization caused by use of the RTOS-embedded system is shown, and an adjustable frame format for a transmission system is described as a measure to avoid the jitter problem. Bit error rate (BER) performances measured in uncorrelated frequency-selective fading channels show that an ST equalizer provides a significantly lower BER than an array processor does.},
keywords={},
doi={},
ISSN={},
month={December},}
Copier
TY - JOUR
TI - Real-Time Multiprocessing System for Space-Time Equalizer in High Data Rate TDMA Mobile Wireless Communications
T2 - IEICE TRANSACTIONS on Communications
SP - 2716
EP - 2725
AU - Takeshi TODA
AU - Masaaki FUJII
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 12
JA - IEICE TRANSACTIONS on Communications
Y1 - December 2002
AB - A new approach to build up a real-time multiprocessing system that is configuration flexible for evaluating space-time (ST) equalizers is described. The core of the system consists of fully programmable devices such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and reduced instruction set computers (RISCs) with a real-time operating system (RTOS). The RTOS facilitates flexibility in the multi-processor configuration for the system conforming with ST processing algorithms. Timing jitter synchronization caused by use of the RTOS-embedded system is shown, and an adjustable frame format for a transmission system is described as a measure to avoid the jitter problem. Bit error rate (BER) performances measured in uncorrelated frequency-selective fading channels show that an ST equalizer provides a significantly lower BER than an array processor does.
ER -