The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Cette lettre présente les résultats d'une série de simulations au niveau de la liaison menées pour évaluer les performances des égaliseurs spatiaux et temporels (égaliseurs S/T) à l'aide de données de mesure de terrain. La configuration de l'égaliseur spatial et temporel discutée dans cette lettre peut être exprimée comme une cascade d'une antenne réseau adaptative et d'un estimateur de séquence de vraisemblance maximale (MLSE) : chacun des éléments d'antenne réseau adaptative possède une ligne à retard à prises fractionnées (FTDL), et le MLSE comporte des prises couvrant une partie du profil de retard de canal. Les performances du taux d'erreur sur les bits (BER) des égaliseurs S/T sont présentées et la sensibilité des performances au décalage temporel des symboles est étudiée.
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Takefumi YAMADA, Shigeru TOMISATO, Tadashi MATSUMOTO, Uwe TRAUTWEIN, "Results of Link-Level Simulations Using Field Measurement Data for an FTDL-Spatial/ MLSE-Temporal Equalizer" in IEICE TRANSACTIONS on Communications,
vol. E84-B, no. 7, pp. 1956-1960, July 2001, doi: .
Abstract: This letter shows the results of a series of link level simulations conducted to evaluate the performances of spatial and temporal equalizers (S/T-equalizers) using field measurement data. The configuration of the spatial and temporal equalizer discussed in this letter can be expressed as a cascade of an adaptive array antenna and maximum likelihood sequence estimator (MLSE): each of the adaptive array antenna elements has a fractionally spaced tapped delay line (FTDL), and the MLSE has taps covering a portion of channel delay profile. Bit error rate (BER) performances of the S/T-equalizers are presented, and performance sensitivity to symbol timing offset is investigated.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e84-b_7_1956/_p
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@ARTICLE{e84-b_7_1956,
author={Takefumi YAMADA, Shigeru TOMISATO, Tadashi MATSUMOTO, Uwe TRAUTWEIN, },
journal={IEICE TRANSACTIONS on Communications},
title={Results of Link-Level Simulations Using Field Measurement Data for an FTDL-Spatial/ MLSE-Temporal Equalizer},
year={2001},
volume={E84-B},
number={7},
pages={1956-1960},
abstract={This letter shows the results of a series of link level simulations conducted to evaluate the performances of spatial and temporal equalizers (S/T-equalizers) using field measurement data. The configuration of the spatial and temporal equalizer discussed in this letter can be expressed as a cascade of an adaptive array antenna and maximum likelihood sequence estimator (MLSE): each of the adaptive array antenna elements has a fractionally spaced tapped delay line (FTDL), and the MLSE has taps covering a portion of channel delay profile. Bit error rate (BER) performances of the S/T-equalizers are presented, and performance sensitivity to symbol timing offset is investigated.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Results of Link-Level Simulations Using Field Measurement Data for an FTDL-Spatial/ MLSE-Temporal Equalizer
T2 - IEICE TRANSACTIONS on Communications
SP - 1956
EP - 1960
AU - Takefumi YAMADA
AU - Shigeru TOMISATO
AU - Tadashi MATSUMOTO
AU - Uwe TRAUTWEIN
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E84-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 2001
AB - This letter shows the results of a series of link level simulations conducted to evaluate the performances of spatial and temporal equalizers (S/T-equalizers) using field measurement data. The configuration of the spatial and temporal equalizer discussed in this letter can be expressed as a cascade of an adaptive array antenna and maximum likelihood sequence estimator (MLSE): each of the adaptive array antenna elements has a fractionally spaced tapped delay line (FTDL), and the MLSE has taps covering a portion of channel delay profile. Bit error rate (BER) performances of the S/T-equalizers are presented, and performance sensitivity to symbol timing offset is investigated.
ER -