The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
La hiérarchie numérique synchrone (SDH) et le réseau optique synchrone (SONET) sont les normes pour les systèmes de transmission d'ondes lumineuses, qui peuvent prendre en charge divers types de signaux existants via des unités tributaires (TU) ou des affluents virtuels (VT). Dans les normes SDH, l'unité tributaire 11 (TU-11) est utilisée pour transporter le signal DS1 avec le pointeur de charge utile et les frais généraux de chemin. Dans cet article, le mappeur TU-11 en mode flottant asynchrone est conçu par des FPGA pour les dispositifs de transmission et de réception. Le signal DS1 est mappé dans la trame TU-11 et via l'interface Combus, puis directement ajouté/déposé dans/depuis la charge utile VC-4 en tirant parti du format de trame d'ordre d'octet de SDH. Dans le sens d'ajout, un synchroniseur doté d'un algorithme de bourrage efficace est conçu pour minimiser la gigue du temps d'attente et absorber le décalage de fréquence, la gigue instantanée, le dérapage et l'écart de la charge utile des données TU-11. Dans le sens de chute, un désynchroniseur mis en œuvre par une nouvelle boucle à verrouillage de phase entièrement numérique et FIFO est utilisé pour s'adapter à l'effet d'espacement irrégulier du format de trame et aux instabilités générées par le mouvement du pointeur et la justification des bits. Un prototype de circuit imprimé est construit avec le mappeur TU-11 conçu et intégré dans un système STM-1 ADM pour des tests à long terme.
SDH, SONNET, DS1, Mappeur TU-11, FPGA
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Yeong-Gang SHOW, Kuo-Bing CHOU, Jim WANG, Kou-Tan WU, "Design of DS1 Transport Device in SDH Network" in IEICE TRANSACTIONS on Communications,
vol. E83-B, no. 7, pp. 1389-1399, July 2000, doi: .
Abstract: Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) are the standards for lightwave transmission systems, which can accommodate various existing signal types via Tributary Units (TUs) or Virtual Tributaries (VTs). In the SDH standards, Tributary Unit-11 (TU-11) is used to transport the DS1 signal with payload pointer and path overheads. In this paper, asynchronous floating mode TU-11 Mapper is designed by FPGAs for transmit and receive devices. The DS1 signal is mapped into TU-11 frame, and through Combus interface, then directly added/dropped into/from the VC-4 payload by taking advantage of the byte order frame format of SDH. In the add direction, a synchronizer with efficient stuffing algorithm is designed to minimize the waiting time jitter and absorb the frequency offset, the instantaneous jitter, the wander, and the gap of TU-11 data payload. In the drop direction, a desynchronizer implemented by a novel all digital phase locked loop and FIFO is used to accommodate the effect of irregular spacing of frame format and jitters generated by the pointer movement and bit justification. A prototype circuit board is built with the designed TU-11 Mapper and embedded in an STM-1 ADM system for long term testing.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e83-b_7_1389/_p
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@ARTICLE{e83-b_7_1389,
author={Yeong-Gang SHOW, Kuo-Bing CHOU, Jim WANG, Kou-Tan WU, },
journal={IEICE TRANSACTIONS on Communications},
title={Design of DS1 Transport Device in SDH Network},
year={2000},
volume={E83-B},
number={7},
pages={1389-1399},
abstract={Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) are the standards for lightwave transmission systems, which can accommodate various existing signal types via Tributary Units (TUs) or Virtual Tributaries (VTs). In the SDH standards, Tributary Unit-11 (TU-11) is used to transport the DS1 signal with payload pointer and path overheads. In this paper, asynchronous floating mode TU-11 Mapper is designed by FPGAs for transmit and receive devices. The DS1 signal is mapped into TU-11 frame, and through Combus interface, then directly added/dropped into/from the VC-4 payload by taking advantage of the byte order frame format of SDH. In the add direction, a synchronizer with efficient stuffing algorithm is designed to minimize the waiting time jitter and absorb the frequency offset, the instantaneous jitter, the wander, and the gap of TU-11 data payload. In the drop direction, a desynchronizer implemented by a novel all digital phase locked loop and FIFO is used to accommodate the effect of irregular spacing of frame format and jitters generated by the pointer movement and bit justification. A prototype circuit board is built with the designed TU-11 Mapper and embedded in an STM-1 ADM system for long term testing.},
keywords={},
doi={},
ISSN={},
month={July},}
Copier
TY - JOUR
TI - Design of DS1 Transport Device in SDH Network
T2 - IEICE TRANSACTIONS on Communications
SP - 1389
EP - 1399
AU - Yeong-Gang SHOW
AU - Kuo-Bing CHOU
AU - Jim WANG
AU - Kou-Tan WU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E83-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 2000
AB - Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) are the standards for lightwave transmission systems, which can accommodate various existing signal types via Tributary Units (TUs) or Virtual Tributaries (VTs). In the SDH standards, Tributary Unit-11 (TU-11) is used to transport the DS1 signal with payload pointer and path overheads. In this paper, asynchronous floating mode TU-11 Mapper is designed by FPGAs for transmit and receive devices. The DS1 signal is mapped into TU-11 frame, and through Combus interface, then directly added/dropped into/from the VC-4 payload by taking advantage of the byte order frame format of SDH. In the add direction, a synchronizer with efficient stuffing algorithm is designed to minimize the waiting time jitter and absorb the frequency offset, the instantaneous jitter, the wander, and the gap of TU-11 data payload. In the drop direction, a desynchronizer implemented by a novel all digital phase locked loop and FIFO is used to accommodate the effect of irregular spacing of frame format and jitters generated by the pointer movement and bit justification. A prototype circuit board is built with the designed TU-11 Mapper and embedded in an STM-1 ADM system for long term testing.
ER -