The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
L'invention concerne un commutateur ATM à arbitrage distribué évolutif (MSDA) multi-QoS qui prend en charge à la fois un trafic à priorité élevée et faible dans le cadre de la discipline de priorité en tête de ligne. Il utilise des tampons de point de croisement et de transit, chacun constitué d'un tampon de priorité élevée et faible. Les buffers arbitrent de manière distribuée la sélection des cellules à transmettre. Le commutateur MSDA prend en charge plusieurs classes de QoS tout en offrant l'évolutivité d'un commutateur SSDA (Scalable-Distributed-Arbitration) à QoS unique décrit précédemment. Un problème survient lorsque le mécanisme de sélection de cellule basé sur le temps de retard utilisé dans le commutateur SSDA est appliqué au trafic de faible priorité : il ne peut pas atteindre l'équité en termes de débit. Ce problème est surmonté en introduisant un mécanisme de sélection de cellules basé sur un arbitre en anneau distribué à chaque point de croisement pour le trafic de faible priorité. Le tampon de transit de faible priorité à chaque point de croisement comporte des files d'attente virtuelles, une pour chaque port d'entrée supérieur. Les cellules destinées au trafic à faible priorité sont sélectionnées par arbitrage en anneau distribué parmi le tampon de point de croisement à faible priorité et ces files d'attente virtuelles. Pour le trafic hautement prioritaire, le même mécanisme de sélection de cellule basé sur le temps de retard est utilisé comme dans le commutateur SSDA. Les simulations montrent que le commutateur MSDA garantit l'équité en termes de temps de retard pour le trafic hautement prioritaire et garantit l'équité en termes de débit pour le trafic faiblement prioritaire.
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Eiji OKI, Naoaki YAMANAKA, Masayoshi NABESHIMA, "Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes" in IEICE TRANSACTIONS on Communications,
vol. E83-B, no. 2, pp. 204-213, February 2000, doi: .
Abstract: A multi-QoS scalable-distributed-arbitration (MSDA) ATM switch is described that supports both high- and low-priority traffic under the head-of-line-priority discipline. It uses crosspoint and transit buffers, each consisting of a high- and low-priority buffer. The buffers arbitrate in a distributed manner the selection of which cellsto transmit. The MSDA switch supports multiple QoS classes while still providing the scalability of a previously described single-QoS scalable-distributed-arbitration (SSDA) switch. A problem occurs when the delay-time-based cell-selection mechanism used in the SSDA switch is applied to the low-priority traffic: it cannot achieve fairness in terms of throughput. This problem is overcome by introducing a distributed-ring-arbiter-based cell-selection mechanism at each crosspoint for the low-priority traffic. The low-priority transit buffer at each crosspoint has virtual queues, one for each upper input port. Cells for the low-priority traffic are selected by distributed-ring arbitration among the low-priority crosspoint buffer and these virtual queues. For the high-priority traffic, the same delay-time-based cell-selection mechanism is used as in the SSDA switch. Simulations show that the MSDA switch ensures fairness interms of delay time for the high-priority traffic and ensures fairness in terms of throughput for the low-priority traffic.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e83-b_2_204/_p
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@ARTICLE{e83-b_2_204,
author={Eiji OKI, Naoaki YAMANAKA, Masayoshi NABESHIMA, },
journal={IEICE TRANSACTIONS on Communications},
title={Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes},
year={2000},
volume={E83-B},
number={2},
pages={204-213},
abstract={A multi-QoS scalable-distributed-arbitration (MSDA) ATM switch is described that supports both high- and low-priority traffic under the head-of-line-priority discipline. It uses crosspoint and transit buffers, each consisting of a high- and low-priority buffer. The buffers arbitrate in a distributed manner the selection of which cellsto transmit. The MSDA switch supports multiple QoS classes while still providing the scalability of a previously described single-QoS scalable-distributed-arbitration (SSDA) switch. A problem occurs when the delay-time-based cell-selection mechanism used in the SSDA switch is applied to the low-priority traffic: it cannot achieve fairness in terms of throughput. This problem is overcome by introducing a distributed-ring-arbiter-based cell-selection mechanism at each crosspoint for the low-priority traffic. The low-priority transit buffer at each crosspoint has virtual queues, one for each upper input port. Cells for the low-priority traffic are selected by distributed-ring arbitration among the low-priority crosspoint buffer and these virtual queues. For the high-priority traffic, the same delay-time-based cell-selection mechanism is used as in the SSDA switch. Simulations show that the MSDA switch ensures fairness interms of delay time for the high-priority traffic and ensures fairness in terms of throughput for the low-priority traffic.},
keywords={},
doi={},
ISSN={},
month={February},}
Copier
TY - JOUR
TI - Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes
T2 - IEICE TRANSACTIONS on Communications
SP - 204
EP - 213
AU - Eiji OKI
AU - Naoaki YAMANAKA
AU - Masayoshi NABESHIMA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E83-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2000
AB - A multi-QoS scalable-distributed-arbitration (MSDA) ATM switch is described that supports both high- and low-priority traffic under the head-of-line-priority discipline. It uses crosspoint and transit buffers, each consisting of a high- and low-priority buffer. The buffers arbitrate in a distributed manner the selection of which cellsto transmit. The MSDA switch supports multiple QoS classes while still providing the scalability of a previously described single-QoS scalable-distributed-arbitration (SSDA) switch. A problem occurs when the delay-time-based cell-selection mechanism used in the SSDA switch is applied to the low-priority traffic: it cannot achieve fairness in terms of throughput. This problem is overcome by introducing a distributed-ring-arbiter-based cell-selection mechanism at each crosspoint for the low-priority traffic. The low-priority transit buffer at each crosspoint has virtual queues, one for each upper input port. Cells for the low-priority traffic are selected by distributed-ring arbitration among the low-priority crosspoint buffer and these virtual queues. For the high-priority traffic, the same delay-time-based cell-selection mechanism is used as in the SSDA switch. Simulations show that the MSDA switch ensures fairness interms of delay time for the high-priority traffic and ensures fairness in terms of throughput for the low-priority traffic.
ER -