The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Une architecture en boucle de DQDB avec réutilisation de slot (LDQDB-SR) segmentée par nœuds d'effacement a été étudiée pour surmonter la limitation de performances due à la nature de l'architecture de bus unidirectionnel de DQDB avec réutilisation de slot. Le LDQDB-SR adopte la libération du slot de destination et une régulation de bande passante inter-segments basée sur le système de file d'attente distribuée de DQDB. Ce réseau souffre non seulement d'une grave détérioration du débit en raison d'un coût de régulation élevé et d'un délai de transit excessif, mais également d'un partage injuste de la bande passante, notamment en cas de surcharge. Dans cet article, nous introduisons une architecture de boucle améliorée de DQDB avec réutilisation des emplacements (ELDQDB-SR) pour améliorer les performances de LDQDB-SR. L'ELDQDB-SR utilise un mécanisme de régulation de la bande passante inter-segments basé sur des quotas pour contrôler efficacement l'utilisation de la bande passante de chaque segment. Chaque station sélectionne le bus qui minimise le nombre de nœuds d'effacement sur le chemin vers les stations de destination. Les méthodes de contrôle d'équité de DQDB sont revues et le mécanisme de réglage alpha est modifié pour obtenir une répartition équitable de la bande passante entre les stations de chaque segment. Les résultats de simulation montrent que l'ELDQDB-SR offre un niveau de débit amélioré et maintient également une bonne équité dans des conditions de surcharge.
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Tae-Joon KIM, Byung-Cheol SHIN, Dong-Ho CHO, "ELDQDB-SR: An Enhanced Loop Architecture of DQDB with Slot Reuse" in IEICE TRANSACTIONS on Communications,
vol. E82-B, no. 7, pp. 1019-1029, July 1999, doi: .
Abstract: A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an inter-segment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alpha-tuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e82-b_7_1019/_p
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@ARTICLE{e82-b_7_1019,
author={Tae-Joon KIM, Byung-Cheol SHIN, Dong-Ho CHO, },
journal={IEICE TRANSACTIONS on Communications},
title={ELDQDB-SR: An Enhanced Loop Architecture of DQDB with Slot Reuse},
year={1999},
volume={E82-B},
number={7},
pages={1019-1029},
abstract={A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an inter-segment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alpha-tuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - ELDQDB-SR: An Enhanced Loop Architecture of DQDB with Slot Reuse
T2 - IEICE TRANSACTIONS on Communications
SP - 1019
EP - 1029
AU - Tae-Joon KIM
AU - Byung-Cheol SHIN
AU - Dong-Ho CHO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E82-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 1999
AB - A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an inter-segment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alpha-tuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions.
ER -